1. Field of the Invention
The present invention relates generally to strained silicon layer structures employed within semiconductor products. More particularly, the present invention relates to enhanced fabrication efficiency strained silicon layer structures employed within semiconductor products.
2. Description of the Related Art
As semiconductor product performance requirements have increased, so also have evolved novel semiconductor materials and structures which provide enhanced semiconductor product performance. Included among such novel materials and structures are strained silicon materials and structures which may be employed as substrates when forming semiconductor devices. Strained silicon materials and structures are desirable as semiconductor substrates insofar as strained silicon materials provide for enhanced carrier mobility and thus enhanced performance of semiconductor devices.
While strained silicon materials and structures are thus desirable in the semiconductor product fabrication art, they are nonetheless not entirely without problems. In that regard, it is often difficult in the semiconductor product fabrication art to efficiently fabricate strained silicon layer structures, insofar as strained silicon layer structures are often fabricated as multi-layer structures with specific laminated material layer requirements.
It is thus desirable in the semiconductor product fabrication art to provide strained silicon layer structures and methods for fabrication thereof, with enhanced fabrication efficiency.
It is towards the foregoing object that the present invention is directed.
Various strained silicon layer structures having desirable properties, and methods for fabrication thereof, have been disclosed in the semiconductor product fabrication art.
Included but not limiting among the strained silicon layer structures and methods, are strained silicon layer structures and methods disclosed within: (1) Ismail et al., in U.S. Pat. No. 5,534,713 (a strained silicon layer structure suitable for fabrication of complementary metal oxide semiconductor (CMOS) field effect transistor (FET) devices); and (2) Chu et al., in U.S. Pat. No. 6,251,751 (a method for forming a bulk and strained silicon on insulator structure by employing selectively oxidizable epitaxial material layers).
The teachings of each of the foregoing references are incorporated herein fully by reference.
Desirable in the semiconductor product fabrication art are additional strained silicon layer structures with enhanced fabrication efficiency.
It is towards the foregoing object that the present invention is directed.